This folder has the script files to synthesize using the XST and implement
the design through command mode or GUI mode.

Steps to run the design using the ise_flow (batch mode):

Windows OS:

1. Double clicking the "ise_flow.bat" file synthesizes the design using
   XST and does the implementation of design.

Linux OS:

1. Run the "ise_flow.sh" command at the prompt as shown below:
   > ./ise_flow.sh

Windows/Linux OS:

2. On running "ise_flow.sh/ise_flow.bat" file, removes the XST report files
   first (if exist any on previous runs) and then does implementation of
   the design.

3. Running the "ise_flow.sh/ise_flow.bat" file creates the ise_flow_results
   text file. It has the report file data for all the XST tool processes.

Steps to run the design using the create_ise (GUI mode - for XST cases only):

1. This file will appear for XST cases only.

2. On executing the "create_ise.sh/create_ise.bat" file creates "test.xise"
   project file and set all the properties of the design selected.

3. The design can be implemented in ISE Projnav GUI by invoking the
   "test.xise" project file.

4. In Linux operating systems, test.xise project can be invoked by executing
   the command 'ise test.xise' from the terminal.

Other files in PAR folder :

* "example_top.ucf" file is the constraint file for the design. This is used
  by ISE tool during translate phase. It has clock constraints, location
  constraints, IO standards and MAXDELAY/SLICE constraints if any.

* "rem_files.sh/rem_files.bat" is called within the ise_flow.sh/ise_flow.bat
   script. This deletes all the previous reports and design files (if any)
   generated by ISE.

* "set_ise_prop.tcl" file has all the properties that needs to be set
  in GUI mode. This file will appear only for XST cases.

* "xst_options.txt" file has synthesis options for the XST tool.
  This file is used for batch mode.

* "icon4_cg.xco", "ddr_ila_basic_cg.xco", "ddr_ila_rdpath_cg.xco",
  "ddr_ila_wrpath_cg.xco" and "ddr_vio_sync_async_out72_cg.xco" files are
  used to generate ChipScope icon, ila and vio EDIF/NGC files. When you want
  to view the design signals on ChipScope, you should port the design signals
  to ChipScope modules i.e. ila, vio and icon and set DEBUG_PORT parameter
  to "ON" in example_top rtl file. In order to generate the EDIF/NGC files,
  you must execute the following commands before starting synthesis and PAR.

        coregen -b icon4_cg.xco
        coregen -b ddr_ila_basic_cg.xco
        coregen -b ddr_ila_rdpath_cg.xco
        coregen -b ddr_ila_wrpath_cg.xco
        coregen -b ddr_vio_sync_async_out72_cg.xco

Note : When you generate the design with DEBUG_PORT = "ON" option, then
       appropriate ChipScope modules must be instantiated in the design top rtl
       file. This folder must contain the necessary ChipScope .ngc files before
       Synthesis and PAR of the design starts.

* At the start of a Chip Scope Analyzer project, all of the signals in
  every core have generic names. "example_top.cdc" is a file that contains
  all the signal names of all cores. Upon importing this file, signal names are
  renamed to the specified names in "example_top.cdc" file. This file will work
  for the generated designs from MIG. If any of the design parameter values
  are changed after generating the design, this file will not work.

Synth folder:

* "example_top.prj" file has commands to add all rtl files to the XST project
  for synthesis.

* "example_top.lso" file is a custom library search order file for XST synthesis.

compatible_ucf folder:

* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI
  (Pin Compatible FPGAs page in GUI). It generates the UCF files for all
  the Compatible FPGAs selected in GUI. If you want to switch to any of the
  Compatible FPGAs follow the steps mentioned below.
