#****************************************************************************
#*                                README
#*
#* Author: Matthew Ballance
#* Desc:   Quick overview of the IVI project
#****************************************************************************

    The IVI project provides an interactive, graphical front-end for 
simulating and debugging Verilog designs.  Currently, IVI is integrated with 
the Icarus Verilog simulator.

    IVI uses a flexible plugin architecture that endevors to make the basic
framework easily configurable and extensible. For example, any simulator
that can provide a VPI interface can be used by IVI.

#********************************************************************
#* Features
#********************************************************************
- Icarus Verilog designs (compiled for VVP) may be loaded
- Design structure may be browsed
- Signals from the design may be added to the waveform window for viewing
- The simulation may be run for an arbitrary time period
- Signals in the waveform window may be viewed in hex, decimal, octal,
  binary, or string radix.
- Cursors may be placed on the waveform window.
- Setup of the waveform window may be saved to a file for later 
  restoration

#********************************************************************
#* Getting Started
#********************************************************************
    It is assumed that IVI has been installed and configured on your 
system (see INSTALL for more information). 
    

#********************************************************************
#* Command Reference
#********************************************************************

#**********************************************************
#* load_design 
#**********************************************************
    This command loads a design and configures IVI to simulate the 
design. Designs may also be loaded via the File->Open->Design menu item.

Format:    load_design <PathToDesign>
Example:   load_design /home/ballance/design.vvp


#**********************************************************
#* run
#**********************************************************
    This command simulates the currently-loaded design. If no design is 
loaded, an error message will be displayed.

Format:    run [$time|forever]
Example:   run 10000   - runs for 10000ns
           run forever - runs until simulation ends


