# Comment line(s) preceding each configuration document the main
# intent behind that configuration, so that we can correctly judge
# whether to preserve that during maintenance decisions.
#
# Other configurations might coincidentally test such configurations
# (e.g. because they are the current default), but it is appropriate
# to intend to teach each feature (or a feature combination) exactly
# once, and for the intent to be reflected precisely in the
# configuration syntax, so that the configurations are stable even
# if the defaults change in future.

# Test on ARM v7
# Test ARM_NEON SIMD
gcc-5 simd=ARM_NEON no-hwloc release-with-assert

# Test on ARM v8
# Test ARM_NEON_ASIMD SIMD
gcc-5 simd=ARM_NEON_ASIMD release-with-assert

# Test the mdrun-only build
# Test newest gcc at time of release
# TODO In combination with gmx from another build, arrange to run regressiontests
gcc-7 mpi no-openmp fftpack mdrun-only

# Test MPMD PME with thread-MPI
# Test oldest supported icc
# Test icc with AVX256 in double precision in release mode
icc-17 simd=avx_256 npme=1 nranks=2 no-openmp  double fftpack release

# Test CUDA build on a agent with no CUDA devices
# Test without TNG support
gcc-4.9 gpuhw=none cuda-10.0 openmp no-tng release-with-assert

# Test non-default GMX_PREFER_STATIC_LIBS behavior
# TODO enable this
# msvc-2017 double no-threadmpi no-prefer-static-libs release-with-assert

# Test with SSE2 + double
# Test newest icc at time of release
icc-19 simd=sse2 double mkl release-with-assert

# Test SSE4.1 SIMD
# Test single-rank GPU
# Test clang + OpenMP + CUDA
clang-4 simd=sse4.1 openmp nranks=1 gpuhw=nvidia cuda-8.0 clang_cuda

# Test MPMD PME with library MPI
# Test clang + OpenMP
clang-5 openmp simd=avx_128_fma npme=1 nranks=2 mpi

# Test SSE2 SIMD
# Test CMAKE_BUILD_TYPE=Release
# Test OpenCL
# Test bundled clFFT (developed by AMD) on NVIDIA OpenCL
gcc-6 npme=1 nranks=2 opencl-1.2 gpuhw=nvidia simd=sse2 release

# Test non-default use of mdrun -gpu_id
# Test GPU-sharing among 4 PP ranks
# Test no hwloc build, tests internal CPU topology detection (mainly for x86)
gcc-5 gpuhw=nvidia nranks=4 gpu_id=1 cuda-8.0 no-hwloc release-with-assert

# Test icc on Windows
# Test icc with SIMD in mixed precision in release mode
icc-18 msvc-2017 fftpack simd=avx2_256 release

# Test ARM HPC compier toolchain with gcc-7
#gcc-7 armhpc-18.2 openmp simd=ARM_NEON_ASIMD release

# Test ARM HPC compier toolchain with armclang
# Test ARMPL for FFTs
# Test linking against ARMPL for BLAS/LAPACK
armclang-18.4 armhpc-18.4 armpl openmp simd=ARM_NEON_ASIMD release-with-assert

# TODO
# Add SIMD + OpenMP + CUDA asan build
# Add OpenMP + CUDA + device sharing TSAN build
# Test statically linked hwloc support (if/when it can work well)
# Test 3D DD (2D is partially covered in regressiontests)
# Test own-fftw build (from local copy of the file)
# Test mdrun -tunepme (e.g. with relaxed tolerances, for now)
# Consider testing of other CMake option paths
# Test behaviour when dlopen is not present
